1. Field of the Invention
The present invention relates to semiconductor packages and fabrication methods thereof, and more particularly, to a flip-chip semiconductor package and a fabrication method thereof.
2. Description of Related Art
Flip-chip technologies facilitate to reduce chip packaging sizes and shorten signal transmission paths and therefore have been widely used for chip packaging. Various types of packages such as chip scale packages (CSPs), direct chip attached (DCA) packages and multi-chip module (MCM) packages can be achieved through flip-chip technologies.
In a flip-chip packaging process, a big CTE (Coefficient of Thermal Expansion) mismatch between a chip and a packaging substrate adversely affects the formation of joints between conductive bumps of the chip and contacts of the packaging substrate, thus easily resulting in delamination of the conductive bumps from the packaging substrate.
On the other hand, along with increased integration of integrated circuits, a CTE mismatch between a chip and a packaging substrate induces more thermal stresses and leads to more serious warpage, thereby reducing the product reliability and resulting in failure of a reliability test.
To overcome the above-described drawbacks, a silicon interposer is disposed between a semiconductor chip and a packaging substrate. Referring to FIG. 1A, a plurality of TSVs 111 are formed in a silicon wafer 10. A redistribution layer 12 is formed on an upper side of the wafer and a plurality of solder balls 13 are formed on a lower side of the wafer. Then, a singulation process is performed to obtain a plurality of silicon interposers 11. Subsequently, a semiconductor chip 14 is disposed on the redistribution layer 12 of a silicon interposer 11 and an underfill 15 is formed between the semiconductor chip 14 and the silicon interposer 11. Then, the silicon interposer 11 is disposed on a substrate 16 and an underfill 17 is formed between the silicon interposer 11 and the substrate 16. As such, a semiconductor package is formed. Since the silicon interposer and the semiconductor chip are made of similar materials, the above-described drawbacks caused by a CTE mismatch can be effectively prevented.
However, the silicon interposer 11 is required to have a plurality of bumps 18 pre-formed thereon so as for the semiconductor chip 14 to be disposed on the silicon interposer 11 through the bumps 18. As such, the bumps 18 between the silicon interposer 11 and the semiconductor chip 14 can be easily affected by temperature variation during the fabrication process, thus easily resulting in cracking at joint interfaces and consequently reducing the product reliability.
FIG. 1B shows a partially enlarged view of FIG. 1A. Referring to FIG. 1B, an UBM (Under Bump Metallurgy) layer 142, a metal post 143 and a nickel layer 144 are sequentially formed on electrode pads 141 of the semiconductor chip 14 and then the nickel layer 144 is bonded to the bumps 18 of the silicon interposer 11 so as to bond the semiconductor chip 14 to the silicon interposer 11. Alternatively, the nickel layer 144 is formed on the bumps 18 and a reflow process is performed to bond the semiconductor chip 14 to the silicon interposer 11. As such, multiple joint interfaces are formed between each of the electrode pads 141 and the corresponding bump 18 of the silicon interposer 11. Since cracking can easily occur at the multiple joint interfaces due to thermal stresses, the product reliability is reduced.
Therefore, there is a need to provide a semiconductor package and a fabrication method thereof so as to overcome the above-described drawbacks.